3d3438 doc #10005 data delay devices, inc. 1 7/8/2010 3 mt. prospect ave. clifton, nj 07013 monolithic 8-bit programmable delay line (series 3d3438) features packages ? all-silicon, low-power cmos technology ? ttl/cmos compatible inputs and outputs ? vapor phase, ir and wave solderable ? leading- and trailing-edge accuracy ? programmable via serial or parallel interface ? increment range: 50ps through 250ps ? delay tolerance: 0.5% (see table 1) ? supply current: 3ma typical ? temperature stability: ? 1.5% max (-40c to 85c) ? vdd stability: ? 0.5% max (3.0v to 3.6v) functional description the 3d3438 device is a versatile 8-bit programmable monolithic delay line. the input (in) is reproduced at the output (out) without inversion, shifted in time as per the user selection. delay values, programmed either via the serial or parallel interface, can be varied over 255 equal steps according to the formula: t i,nom = t inh + i * t inc where i is the programmed address, t inc is the delay increment (equal to the device dash number), and t inh is the inherent (address zero) delay. the device features both rising- and falling-edge accuracy. the all-cmos 3d3438 integrated circuit has been designed as a reliable, economic alternative to hybrid ttl programmable delay lines. it is offered in a standard surface mount 16-pin sol. an 8-pin soic package is available for applications where the parallel interface is not needed. similarly, a 14-pin soic is offered for applications where the serial interface is not needed. table 1: part number specifications part delays and tolerances input restrictions number inherent delay (ns) delay range (ns) delay step (ps) max freq (addr=0) max freq (addr=255) min p.width (addr=0) min p.width (addr=255) 3d3438x-50 7.0 ? 0.5 12.750 ? .05 50 ? 25 150 mhz 98 mhz 3.3 ns 5.1 ns 3d3438x-60 7.0 ? 0.5 15.300 ? .06 60 ? 30 150 mhz 82 mhz 3.3 ns 6.1 ns 3d3438x-75 7.0 ? 0.5 19.125 ? .08 75 ? 38 150 mhz 65 mhz 3.3 ns 7.6 ns 3d3438x-80 7.0 ? 0.5 20.400 ? .08 80 ? 40 150 mhz 61 mhz 3.3 ns 8.1 ns 3d3438x-100 7.0 ? 0.5 25.500 ? .10 100 ? 50 150 mhz 49 mhz 3.3 ns 10.0 ns 3d3438x-125 7.0 ? 0.5 31.875 ? .13 125 ? 63 150 mhz 39 mhz 3.3 ns 12.7 ns 3d3438x-150 7.0 ? 0.5 38.250 ? .15 150 ? 75 150 mhz 32 mhz 3.3 ns 15.3 ns 3d3438x-200 7.0 ? 0.5 51.000 ? .20 200 ? 100 150 mhz 24 mhz 3.3 ns 20.4 ns 3D3438X-250 7.0 ? 0.5 63.750 ? .25 250 ? 125 150 mhz 19 mhz 3.3 ns 25.5 ns notes: replace the ?x? in the part number with d, s or z, depending on choice of package. any dash number between 50 and 250 not shown is also available as standard. see application notes section for more details ? 2010 data delay devices pin descriptions in signal input out signal output md mode select ae address enable p0-p7 parallel data input sc serial clock si serial data input so serial data output vdd +3.3 volts gnd ground 1 2 3 4 8 7 6 5 in so ae gnd vdd out sc si 3d3438z-xx soic8 3d3438d-xx soic14 1 2 3 4 5 6 7 14 13 12 11 10 9 8 in ae p0 p1 p2 p3 gnd vdd out p7 p6 p5 p4 gnd 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 in ae so/p0 p1 p2 p3 p4 gnd vdd out md p7 p6 sc p5 si 3d3438s-xx sow16 for mechanical dimensions, click here . for package marking details, click here . su p er-fine resolution
3d3438 doc #10005 data delay devices, inc. 2 7/8/2010 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com application notes general information the 8-bit programmable 3d3438 delay line architecture is comprised of a sequence of five identical delay cells connected in series, all of which are controlled by a common current. this current, in turn, is controlled by the user-selected programming data (the address). the delay cells produce at their output a replica of the signal present at the input, shifted in time. the change in delay from one address setting to the next is called the increment , or lsb. it is nominally equal to the device dash number. the minimum delay, achieved by setting the address to zero, is called the inherent delay . for best performance, it is essential that the power supply pin be adequately bypassed and filtered. in addition, the power bus should be of as low an impedance construction as possible. power planes are preferred. also, signal traces should be kept as short as possible. delay accuracy there are a number of ways of characterizing the delay accuracy of a programmable line. the first is the differential nonlinearity (dnl), also referred to as the increment error. it is defined as the deviation of the increment at a given address from its nominal value. for all dash numbers, the dnl is within 0.5 lsb at every address (see table 1: delay step). the integrated nonlinearity (inl) is determined by first constructing t he least-squares best fit straight line through the delay-versus-address data. the inl is then the deviation of a given delay from this line. for all dash numbers, the inl is within 1.0 lsb at every address. the relative error is defined as follows: e rel = (t i ? t 0 ) ? i * t inc where i is the address, t i is the measured delay at the i?th address, t 0 is the measured inherent delay, and t inc is the nominal increment. it is very similar to the inl, but simpler to calculate. for all dash numbers, the relative error is less than 1.0 lsb at every address (see table 1: delay range). the absolute error is defined as follows: e abs = t i ? (t inh + i * t inc ) where t inh is the nominal inherent delay. the absolute error is limited to 1.5 lsb or 1.0 ns, whichever is greater, at every address. the inherent delay error is the deviation of the inherent delay from its nominal value. for all dash numbers, it is limited to 0.5 ns. delay stability the delay of cmos integrated circuits is strongly dependent on power supply and temperature. the 3d3438 utilizes novel compensation circuitry to minimize the delay variations induced by fluctuations in power s upply and/or temperature. the 3d3438 is designed to be most stable at the maximum address setting (255). at this operating condition, the thermal coefficient of the absolute delay is limited to ? 250 ppm/c, which is equivalent to a variation, over the -40c to 85c operating range, of ? 1.5% from the room- temperature delay. at smaller address settings the thermal coefficient will be somewhat larger. at the maximum address, the power supply sensitivity of the absolute delay is ? 0.5% over the 3.0v to 3.6v operating range, with respect to the delay at the nominal 3.3v power supply. at smaller address settings the sensitivity will be somewhat larger. input signal characteristics the maximum input frequency and minimum input pulse width are bot h limited by the device. exceeding either limit will cause the signal to be blocked by the line. furthermore, for a given device, these limitations vary with the user- specified address. the relationships are: f max = 1250 / (i * t inc ) pw min = 0.4 * (i * t inc ), where f max is in mhz, and pw min & t inc are in ns. these relationships break down for small delays: f max can never be greater than 150 mhz, and pw min can never be smaller than 3.3 ns. programming interface figure 1 illustrates the main functional blocks of the 3d3438 delay program interface. since the 3d3438 is a cmos design, all unused input pins must be returned to well defined logic levels, vdd or ground.
3d3438 doc #10005 data delay devices, inc. 3 7/8/2010 3 mt. prospect ave. clifton, nj 07013 application notes (cont?d) transparent parallel mode (md = 1, ae = 1) the eight program pins p0 - p7 directly control the output delay. a change on one or more of the program pins will be reflected on the output delay after a time t pdv , as shown in figure 2. a register is required if the programming data is bused. latched parallel mode (md = 1, ae pulsed) the eight program pins p0 - p7 are loaded by the falling edge of the enable pulse, as shown in figure 3. after each change in delay value, a settling time t edv is required before the input is accurately delayed. serial mode (md = 0) while observing data setup ( t dsc ) and data hold ( t dhc ) requirements, timing data is loaded in msb-to-lsb order by the rising edge of the clock (sc) while the enable (ae) is high, as shown in figure 4. the falling edge of the enable (ae) activates the new delay value which is reflected at the output after a settling time t edv . as data is shifted into the serial data input (si), the previous contents of the 8-bit input register are shifted out of the serial output port pin (so) in msb-to-lsb order, thus allowing cascading of multiple devices by connecting the serial output pin (so) of the preceding device to the serial data input pin (si) of the succeeding device, as illustrated in figure 5. the total number of serial data bits in a cascade configuration must be eight times the number of units, and each group of eight bits must be transmitted in msb-to-lsb order. to initiate a serial read, enable (ae) is driven high. after a time t eqv , bit 7 (msb) is valid at the serial output port pin (so). on the first rising edge of the serial clock (sc), bit 7 is loaded with the value present at the serial data input pin (si), while bit 6 is presented at the serial output pin (so). to retrieve the remaining bits seven more rising edges must be generated on the serial clock line. the read operation is destructive. therefore, if it is desired that the original delay setting remain unchanged, the read data must be written back to the device(s) before the enable (ae) pin is brought low. the so pin, if unused, must be allowed to float if the device is configured in the serial programming mode. the serial mode is the only mode available on the 8-pin version of the 3d3438, and this mode is unavailable on the 14-pin version of the 3d3438. programmable delay line latch 8-bit input register md sc si a e in so out p0 p1 p2 p3 p4 p5 p6 p7 mode select shift clock serial input a ddress enable signal in signal out serial output parallel inputs figure1: functional block diagram previous previous new value new value t pdx t pdv parallel inputs p0-p7 delay time figure 2: non-latched parallel mode (md=1, ae=1)
3d3438 doc #10005 data delay devices, inc. 4 7/8/2010 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com application notes (cont?d) previous new value new value t edx t edv parallel inputs p0-p7 delay time t dse t dhe t ew enable (ae) figure 3: latched parallel mode (md=1) new value new bit 7 new bit 0 new bit 6 old bit 7 old bit 6 old bit 0 enable (ae) clock (sc) serial input ( si ) serial output ( so ) delay time t ew t es t cw t cw t eh t dsc t dhc t egv t cqv t cqx t eqz t edv t edx previous value figure 4: serial mode (md=0) from writing device to next device si so sc ae 3d3438 3d3438 3d3438 figure 5: cascading multiple devices si so sc ae si so sc ae table 2: delay vs. programmed address programmed address nominal delay (ns) per 3d3438 dash number parallel p7 p6 p5 p4 p3 p2 p1 p0 serial msb lsb -50 -75 -100 -125 -150 -200 -250 step 0 0 0 0 0 0 0 0 0 7.000 7.000 7.000 7.000 7.000 7.000 7.000 step 1 0 0 0 0 0 0 0 1 7.050 7.075 7.100 7.125 7.150 7.200 7.250 step 2 0 0 0 0 0 0 1 0 7.100 7.150 7.200 7.250 7.300 7.400 7.500 step 3 0 0 0 0 0 0 1 1 7.150 7.225 7.300 7.375 7.450 7.600 7.750 step 4 0 0 0 0 0 1 0 0 7.200 7.300 7.400 7.500 7.600 7.800 8.000 step 5 0 0 0 0 0 1 0 1 7.250 7.375 7.500 7.625 7.750 8.000 8.250 step 253 1 1 1 1 1 1 0 1 19.650 25.975 32.300 38.625 44.950 57.600 70.250 step 254 1 1 1 1 1 1 1 0 19.700 26.050 32.400 38.750 45.100 57.800 70.500 step 255 1 1 1 1 1 1 1 1 19.750 26.125 32.500 38.875 45.250 58.000 70.750 change 12.750 19.125 25.500 31.875 38.250 51.000 63.750
3d3438 doc #10005 data delay devices, inc. 5 7/8/2010 3 mt. prospect ave. clifton, nj 07013 device specifications table 3: absolute maximum ratings parameter symbol min max units notes dc supply voltage v dd -0.3 7.0 v input pin voltage v in -0.3 v dd +0.3 v input pin current i in -10 10 ma 25c storage temperature t strg -55 150 c lead temperature t lead 300 c 10 sec table 4: dc electrical characteristics (-40c to 85c, 3.0v to 3.6v) parameter symbol min typ max units notes static supply current* i dd 3.0 5.0 ma addr = 128 high level input voltage v ih 2.0 v low level input voltage v il 0.8 v high level input current i ih 1.0 ? a v ih = v dd low level input current i il 1.0 ? a v il = 0v high level output current i oh -15.0 -4.0 ma v dd = 3.0v v oh = 2.4v low level output current i ol 4.0 15.0 ma v dd = 3.0v v ol = 0.4v output rise & fall time t r & t f 2.0 2.5 ns c ld = 5 pf *i dd (dynamic) = c ld * v dd * f input capacitance = 10 pf typical where: c ld = average capacitance load/line (pf) output load capacitance (c ld ) = 25 pf max f = input frequency (ghz) table 5: ac electrical characteristics (-40c to 85c, 3.0v to 3.6v) parameter symbol min typ max units notes clock frequency f c 80 mhz enable width t ew 10 ns clock width t cw 10 ns data setup to clock t dsc 10 ns data hold from clock t dhc 3 ns data setup to enable t dse 10 ns data hold from enable t dhe 3 ns enable to serial output valid t eqv 20 ns enable to serial output high-z t eqz 20 ns clock to serial output valid t cqv 20 ns clock to serial output invalid t cqx 10 ns enable setup to clock t es 10 ns enable hold from clock t eh 10 ns parallel input valid to delay valid t pdv 20 40 ns parallel input change to delay invalid t pdx 0 ns enable to delay valid t edv 35 45 ns enable to delay invalid t edx 0 ns input pulse width t wi 40 % of delay see table 1 input period period 80 % of delay see table 1 input to output delay t plh , t phl ns see table 2
3d3438 doc #10005 data delay devices, inc. 6 7/8/2010 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com silicon delay line automated testing test conditions input: output: ambient temperature: 25 o c ? 3 o c r load : 10k ? ? 10% supply voltage (vcc): 5.0v ? 0.1v c load : 5pf ? 10% input pulse: high = 3.0v ? 0.1v threshold: 1.5v (rising & falling) low = 0.0v ? 0.1v source impedance: 50 ? max. rise/fall time: 3.0 ns max. (measured between 0.6v and 2.4v ) pulse width: pw in = 2 x max delay period: per in = 10 x max delay note: the above conditions are for test only and do not in any way restrict the operation of the device. out trig in ref trig figure 6: test setup device under test (dut) digital scope/ time interval counter pulse generator out in computer system printer figure 7: timing diagram t plh t phl per in pw in t rise t fall 0.6 0.6 1.5 1.5 2.4 2.4 1.5 1.5 v ih v il v oh v ol input signal output signal 10k ? 470 ? 5pf device under test digital scope
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